1. Field of the Invention
This invention relates to a power down type address buffer circuit which suspends power consumption during a stand-by period.
2. Description of the Prior Art
Generally, in a RAM (Random Access Memory) where memory cells are arranged in the form of a matrix, a memory cell is selected in accordance with outputs of row and column address decoders. These address decoders are generally composed of NOR gates and applied to the NOR gates are specified signals from among the in-phase internal address signals and inverse-phase internal address signals generated from an external address input in address buffer circuits. Recently, in view of efforts towards reducing power consumption, the address buffer circuit is often so designed that the power consumption of the circuits is suspended during the stand-by period by means of a signal generated from an external chip select input signal. In such a power-down type address buffer circuit, the output timing differs according to the relation betwen an external chip select input signal and an external address input signal. This difference is generally a very short period and it is not a problem when the chip select access is faster than the adddress access, but when the chip select access becomes slower than the address access because of the circuit design, the difference causes a slower the access time for the memory.